As numbers of computers, particularly servers, are deployed in large-scale or hyper-scale data center applications, the need to connect those computers to one another at massive scale as well as connecting them to the outside world has driven change in data center networking topologies and strategies. Two of the primary drivers of cost and performance in these large networks are the network topology and the photonic interconnections between them. The trend has been to utilize many low-cost, low-radix switches that are connected to other low-radix switches via many connections, both copper and optical.
As the networks increase efficiency by increasing data rate, the distances that can be traversed by copper cables are diminished. As a result, cost-reduction exercises have developed high-channel-count solutions that amortize the cost of cable attachment and packaging across a larger number of connections. Where current solutions may use optical engines with 4 channels or perhaps 8 channels, these high-density solutions favor 24-36 channels.
Taking 24-channel or 36-channel cables directly to computer servers is not efficient due to overprovisioning. Likewise, taking 4-channel solutions to many servers is not efficient due to duplicative packaging costs. As more networks seeks to use high-radix switches in order to remove layers from the network hierarchy, they are challenged by the costs of the final layer connection to the servers. Since the connections between a high-radix middle-of-row (MOR) switch and a large array of servers requires making many connections, and those servers are in different equipment racks, the problem of requiring the distance capabilities of optical connections is conflated with the problem of requiring low-cost connections to many servers.
There is an additional complexity having to do with bandwidth and data rate. The chips generally used in the network switches tend to utilize 50 gigabyte (50G) pulse amplitude modulation with 4 encoding levels (PAM-4 I/O) structures. At the server level, the network interface controller (NIC) card generally includes a network acceleration field programmable gate arrays (FPGA) run at 25G non-return to zero (NRZ). Therefore, a 2:1 data rate ratio is needed between the network switch and the server. This is commonly accomplished by use of retime and/or gearbox devices that accommodate high data rate on one side and provide twice as many channels at half the data rate on the other side.
The figures are not exhaustive and do not limit the present disclosure to the precise form disclosed.